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IP core portfolio

Fifteen licensable cores across three families. Every entry below ships with the same deliverable set — portable VHDL, a bit-accurate reference model, a UVM verification environment and synthesis collateral for FPGA and ASIC targets.

15 cores
Part number Core Headline specification Targets Status Documentation
Wireless & Satellite Modems
ALF-RF-S2X-TX DVB-S2/S2X modulator MODCOD 1–128, VCM/ACM, roll-off 5–35 %, up to 500 Msym/s FPGA · ASIC Production Datasheet
ALF-RF-S2X-RX DVB-S2/S2X demodulator Acquisition to −10 dB Es/N0, wideband carrier search, pilot-aided FPGA · ASIC Production Datasheet
ALF-RF-NR-PHY 5G NR gNB Layer-1 PHY FR1/FR2, 100 MHz CC, up to 4×4 MIMO, Release 17 numerologies FPGA · ASIC Production Datasheet
ALF-RF-QAM QAM modem 16-QAM to 256-APSK, blind acquisition, 1 ksym/s – 250 Msym/s FPGA · ASIC Production Datasheet
ALF-RF-PSK PSK modem BPSK to 16-PSK, acquisition to −5 dB Es/N0, up to 300 Msym/s FPGA · ASIC Production Datasheet
ALF-RF-CPM CPM / GMSK / SOQPSK modem IRIG-106 and CCSDS profiles, full and partial response FPGA Production Datasheet
ALF-RF-CCSDS CCSDS telemetry & telecommand modem 131.0-B / 231.0-B, GMSK and filtered OQPSK, ranging support FPGA · rad-tolerant Production Datasheet
ALF-RF-OFDM Configurable OFDM transceiver framework User-defined frame structure, pilot pattern and FFT size FPGA · ASIC In development Datasheet
Digital Front-End
ALF-RF-DPD Adaptive digital pre-distortion GMP and DDR models, 400 MHz instantaneous BW, > 20 dB ACLR gain FPGA · ASIC Production Datasheet
ALF-RF-DDC Multi-carrier digital down-converter Up to 16 carriers, decimation 2–4096, independent NCO per carrier FPGA · ASIC Production Datasheet
ALF-RF-DUC Multi-carrier digital up-converter Up to 16 carriers, interpolation 2–4096, 491.52 MSPS output FPGA · ASIC Production Datasheet
ALF-RF-FRS Arbitrary fractional resampler Farrow structure, ratio 0.25–4.0, > 90 dB image rejection FPGA · ASIC Production Datasheet
Channel Coding & FEC
ALF-RF-LDPC-ENC LDPC encoder 5G NR BG1/BG2, DVB-S2X and CCSDS matrices, up to 40 Gbps FPGA · ASIC Production Datasheet
ALF-RF-LDPC-DEC LDPC decoder Layered normalised min-sum, up to 25 Gbps, early termination FPGA · ASIC Production Datasheet
ALF-RF-VITERBI Convolutional encoder / Viterbi decoder K = 5–9, punctured rates 1/2–7/8, hard and soft decision FPGA · ASIC Production Datasheet
Looking for PCI Express, converter links or SoC infrastructure? Those are our sister company's catalogue. alfacores licenses them on the same terms, with the same deliverables, and the two portfolios are built to be used together.
Headline figures are configuration-dependent. The numbers above come from a specific parameter set on a specific target. Every datasheet carries the full resource, latency and throughput equations so you can compute the figure for your configuration before you commit. Request the datasheet for any part number.

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