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Channel coding & FEC cores

Forward error correction is where link budget is won and where area is lost. Every decoder in this family exposes throughput, latency and iteration count as independent build-time choices, and every one ships with the BER and BLER curves that produced its published coding gain — generated by the same testbench you receive.

A note on decoder throughput figures. Published LDPC and turbo throughput almost always assumes early termination on clean data. Our datasheets give throughput at a stated iteration count and the worst case with early termination disabled, because that is the number your buffer sizing actually depends on.
ALF-RF-LDPC-ENC

LDPC EncoderMulti-standard low-density parity-check encoding

Production Datasheet

Encoder covering the 3GPP, DVB and CCSDS LDPC code families from a single parameterised architecture. Parity computation is scheduled from a compact description of the base graph rather than a flattened matrix, so adding or switching a code set costs memory rather than logic.

  • 3GPP 38.212 base graphs 1 and 2, all lifting sizes
  • DVB-S2X normal, short and VL-SNR frame codes
  • CCSDS 131.0-B AR4JA and C2 codes
  • Rate matching, bit selection and interleaving included
  • Parallelism selectable from 1 to 384 bits per cycle
  • Multi-codeword pipelining with no inter-frame gap

Key specifications

Standards3GPP 38.212, DVB-S2X, CCSDS 131.0-B
ThroughputUp to 40 Gbps
Code rates1/5 – 8/9 depending on standard
Parallelism1 – 384 bits/cycle (build-time)
LatencyZ + 24 cycles per codeword (NR, Z = lifting size)
InterfacesAXI4-Stream data, AXI4-Lite control
Typical FPGA12 kLUT, 0.7 Mb BRAM @ 400 MHz
Multi-standard 40 Gbps Silicon-proven
Read the ALF-RF-LDPC-ENC datasheet
ALF-RF-LDPC-DEC

LDPC DecoderLayered normalised min-sum decoding

Production Datasheet

Layered decoder with normalised min-sum check-node processing. Layered scheduling roughly halves the iteration count needed for a given BER against flooding, which is the dominant term in both throughput and energy per bit. Message width, normalisation factor and maximum iteration count are all parameters, and the datasheet gives the BER cost of each choice.

  • Layered normalised min-sum with configurable offset
  • Early termination on parity check with programmable threshold
  • Message quantisation 4 – 8 bits, BER impact characterised
  • Multi-core instantiation for throughput scaling
  • Per-codeword iteration count and syndrome weight reported
  • Optional layered-flooding hybrid for very low latency modes

Key specifications

Standards3GPP 38.212, DVB-S2X, CCSDS 131.0-B
ThroughputUp to 25 Gbps (8 iterations, 4 instances)
Iterations1 – 50, early termination
Quantisation4 – 8 bit LLR
Coding gain loss< 0.15 dB vs. floating-point sum-product
InterfacesAXI4-Stream data, AXI4-Lite control
Typical FPGA68 kLUT, 6.2 Mb BRAM @ 400 MHz
Layered NMS Early termination Silicon-proven
Read the ALF-RF-LDPC-DEC datasheet
ALF-RF-VITERBI

Convolutional Encoder / Viterbi DecoderConfigurable constraint length and puncturing

Production Datasheet

General-purpose convolutional codec. Generator polynomials, constraint length, puncturing pattern and traceback depth are all parameters, so the same core covers the legacy DVB inner code, the 802.11 BCC path, CCSDS rate-1/2 K=7 and proprietary codes without a source change.

  • Constraint length 5 – 9, arbitrary generator polynomials
  • Punctured rates 1/2 through 7/8, user-defined patterns
  • Hard and soft decision input, 1 – 8 bit soft quantisation
  • Register-exchange or traceback survivor memory
  • Tail-biting and zero-terminated modes
  • Radix-2 and radix-4 butterfly options for throughput scaling

Key specifications

Constraint length5 – 9
Code rate1/2 – 7/8 with puncturing
ThroughputUp to 2.4 Gbps (K = 7, radix-4, 8 bits/cycle)
Traceback depthConfigurable, typically 5 × K
ModesTail-biting and zero-terminated
InterfacesAXI4-Stream data, AXI4-Lite control
Typical FPGA6.8 kLUT, 0.3 Mb BRAM @ 400 MHz
Configurable Tail-biting Silicon-proven
Read the ALF-RF-VITERBI datasheet

Bring us your BER target.

Tell us the required BER at a given Es/N0, the throughput and the resource envelope. We will tell you which code and which configuration meets all three — or that no configuration does.

Discuss your link budget Back to portfolio