Document
ALF-DS-RFS2XTX
Revision
0.1
Date
July 2026
Status
Preliminary — draft
Preliminary draft. This document is an outline datasheet issued for evaluation and planning. Specifications are subject to change and the figures given are for a representative configuration on a representative target. Request the released datasheet for the complete parameter list, characterisation curves and interface timing.

1  Overview

Full DVB-S2X transmit chain from BBFRAME input to shaped IQ output: mode adaptation, stream merging, BCH and LDPC encoding, bit interleaving, constellation mapping, physical-layer framing with pilot insertion, and SRRC pulse shaping. Variable and adaptive coding and modulation are driven per frame from the control plane, so a scheduler can change MODCOD on a frame boundary without a datapath flush.

2  Features

  • All 128 S2X MODCODs plus the legacy S2 set, including VL-SNR frames
  • VCM, ACM and CCM operation with per-frame MODCOD selection
  • Roll-off 35 %, 25 %, 20 %, 15 %, 10 % and 5 %
  • Optional wideband mode: up to 500 Mbaud on a single carrier
  • Physical-layer scrambling with programmable gold-code index
  • Built-in DVB-S2X compliant test-pattern generator

3  Applications

  • Satellite gateways, VSAT terminals and on-board processors
  • Cellular base stations and private network radios
  • Software-defined and tactical radios
  • Telemetry, ranging and instrumentation links

4  Specifications

Figures below are for a representative configuration. Resource, latency and throughput scale with the build-time parameters; the released datasheet gives each as a closed-form function of those parameters so you can compute the number for your own configuration.

StandardsETSI EN 302 307-1 / -2
Symbol rate100 ksym/s – 500 Msym/s
Modulationπ/2-BPSK to 256-APSK
Frame typesNormal (64 800), short (16 200), VL-SNR
Latency1 FECFRAME + 212 clock cycles
InterfacesAXI4-Stream data, AXI4-Lite control
Typical FPGA34 kLUT, 62 DSP, 2.1 Mb BRAM @ 250 MHz
Product familyWireless & Satellite Modems
AvailabilityProduction

5  Interfaces and control

The core presents AXI4-Stream data, AXI4-Lite control. All streaming interfaces follow the AXI4-Stream handshake with full back-pressure support; the control plane is generated by ALF-CR-REGGEN, so the register map in section 5 is generated from the same source as the delivered VHDL and cannot drift from it.

The register map is delivered as an IP-XACT description alongside a C header and a UVM register abstraction layer, all generated together. Every field carries its access policy, reset value and any side effect in the generated documentation.

6  Configuration

The core is configured through a single package file of build-time parameters and an elaboration-time consistency check that fails the build — rather than failing in simulation — when a parameter combination is not supported. There is no source fork per configuration, so you stay on the mainline release and keep receiving maintenance updates.

Re-parameterisation within the documented range is covered by your licence at no additional cost. If you need a parameter outside the documented range, that is a design services conversation rather than a new licence.

7  Verification

ALF-RF-S2X-TX is signed off against the release criteria described on the quality page: bit-exact agreement with the reference model across the regression suite, 100 % statement, branch and toggle coverage with every exclusion reviewed, formal proof of deadlock freedom and reset correctness on the control logic, and timing closure with positive slack on every supported target from the delivered constraints.

The verification environment used for that sign-off is part of the deliverable set. You can re-run it against your own configuration on your own farm.

8  Deliverables

VHDL sourceSynthesisable VHDL-2008, readable and commented, lint-clean
Closed-box alternativeEncrypted netlist or protected model, where source is not licensed
Reference modelBit-accurate C++ (Python bindings) or MATLAB, with stimulus scripts
VerificationUVM testbench, functional coverage model, interface assertions
Test vectorsDirected and constrained-random sets with expected outputs
SynthesisTiming constraints, build scripts and reference reports per target
Example designBuildable project instantiating the core in a system context
DocumentationDatasheet, integration guide, register map, interface timing
SoftwareBare-metal C driver and Linux reference driver, where applicable

9  Licensing and ordering

ALF-RF-S2X-TX is available under single-project, multi-project, evaluation and academic licences. All models are one-time fees with no per-unit royalty. See licensing for the full terms, or request a quotation quoting this part number.

10  Document revision history

RevisionDateChange
0.1July 2026Initial preliminary draft