1 Overview
Encoder covering the 3GPP, DVB and CCSDS LDPC code families from a single parameterised architecture. Parity computation is scheduled from a compact description of the base graph rather than a flattened matrix, so adding or switching a code set costs memory rather than logic.
2 Features
- 3GPP 38.212 base graphs 1 and 2, all lifting sizes
- DVB-S2X normal, short and VL-SNR frame codes
- CCSDS 131.0-B AR4JA and C2 codes
- Rate matching, bit selection and interleaving included
- Parallelism selectable from 1 to 384 bits per cycle
- Multi-codeword pipelining with no inter-frame gap
3 Applications
- Satellite and space communication links
- Cellular base-station physical layers
- Point-to-point microwave and proprietary links
- Storage and optical transport systems
4 Specifications
Figures below are for a representative configuration. Resource, latency and throughput scale with the build-time parameters; the released datasheet gives each as a closed-form function of those parameters so you can compute the number for your own configuration.
| Standards | 3GPP 38.212, DVB-S2X, CCSDS 131.0-B |
|---|---|
| Throughput | Up to 40 Gbps |
| Code rates | 1/5 – 8/9 depending on standard |
| Parallelism | 1 – 384 bits/cycle (build-time) |
| Latency | Z + 24 cycles per codeword (NR, Z = lifting size) |
| Interfaces | AXI4-Stream data, AXI4-Lite control |
| Typical FPGA | 12 kLUT, 0.7 Mb BRAM @ 400 MHz |
| Product family | Channel Coding & FEC |
| Availability | Production |
5 Interfaces and control
The core presents AXI4-Stream data, AXI4-Lite control. All streaming interfaces follow the AXI4-Stream handshake with full back-pressure support; the control plane is generated by ALF-CR-REGGEN, so the register map in section 5 is generated from the same source as the delivered VHDL and cannot drift from it.
The register map is delivered as an IP-XACT description alongside a C header and a UVM register abstraction layer, all generated together. Every field carries its access policy, reset value and any side effect in the generated documentation.
6 Configuration
The core is configured through a single package file of build-time parameters and an elaboration-time consistency check that fails the build — rather than failing in simulation — when a parameter combination is not supported. There is no source fork per configuration, so you stay on the mainline release and keep receiving maintenance updates.
Re-parameterisation within the documented range is covered by your licence at no additional cost. If you need a parameter outside the documented range, that is a design services conversation rather than a new licence.
7 Verification
ALF-RF-LDPC-ENC is signed off against the release criteria described on the quality page: bit-exact agreement with the reference model across the regression suite, 100 % statement, branch and toggle coverage with every exclusion reviewed, formal proof of deadlock freedom and reset correctness on the control logic, and timing closure with positive slack on every supported target from the delivered constraints.
The verification environment used for that sign-off is part of the deliverable set. You can re-run it against your own configuration on your own farm.
8 Deliverables
| VHDL source | Synthesisable VHDL-2008, readable and commented, lint-clean |
|---|---|
| Closed-box alternative | Encrypted netlist or protected model, where source is not licensed |
| Reference model | Bit-accurate C++ (Python bindings) or MATLAB, with stimulus scripts |
| Verification | UVM testbench, functional coverage model, interface assertions |
| Test vectors | Directed and constrained-random sets with expected outputs |
| Synthesis | Timing constraints, build scripts and reference reports per target |
| Example design | Buildable project instantiating the core in a system context |
| Documentation | Datasheet, integration guide, register map, interface timing |
| Software | Bare-metal C driver and Linux reference driver, where applicable |
9 Licensing and ordering
ALF-RF-LDPC-ENC is available under single-project, multi-project, evaluation and academic licences. All models are one-time fees with no per-unit royalty. See licensing for the full terms, or request a quotation quoting this part number.
10 Document revision history
| Revision | Date | Change |
|---|---|---|
| 0.1 | July 2026 | Initial preliminary draft |