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System solutions
Finished instruments, not licensable blocks. Each system is an FPGA hardware platform built from the same IP cores we license — which is why the real-time behaviour is deterministic and the specifications are the ones we already characterise for the cores inside.
Test equipment for radio development
Both systems exist because a customer needed something the general-purpose instrument market did not offer at a sensible price: hard real-time behaviour, and protocol accuracy without a host PC in the loop.
RF Channel Emulator
Reproduces what the propagation environment does to your signal — fading, delay, Doppler, noise, interference and hardware impairments — deterministically and repeatably, entirely in FPGA fabric.
- Sub-microsecond end-to-end processing latency
- Real-time FPGA implementation, no host in the datapath
- Up to 400 MHz emulation bandwidth per channel
- Bit-repeatable scenarios for regression testing
Vector Signal Generator
Generates standards-compliant waveforms as the standard actually defines them — full framing, coding and signalling — and runs standalone, without a PC, a licence dongle or a per-waveform option key.
- Protocol-accurate generation, not a replayed capture
- Fully standalone operation from the front panel
- Continuous generation with no waveform memory limit
- Closed-loop impairment injection on request
Real time is a property, not a marketing word
Both systems process every sample in fabric, on a fixed clock, with a fixed pipeline. Nothing in the signal path is scheduled by software.
- Deterministic latency Latency is a fixed number of clock cycles, not a statistical distribution. It is the same on the first sample and the ten-billionth, and it does not change because the host machine was busy. For closed-loop testing — where the device under test reacts to what the instrument produces — this is the difference between a valid test and a meaningless one.
- No sample loss, ever A software-defined instrument that drops samples under load produces results that look plausible and are wrong. In fabric there is no scheduler to preempt the datapath and no buffer that can underrun; the pipeline either meets timing at build or it does not build.
- Repeatability by construction All stochastic processes are driven by seeded generators in hardware. Re-run a scenario with the same seed and you get the identical sample stream — which is what makes a failure reproducible and a regression suite meaningful.
- Built from characterised cores The processing inside is our own licensed IP — the same front-end, modem and channel coding cores, with the same verification behind them. Nothing in these instruments is a block we cannot explain.
How systems are supplied
Systems are quoted per configuration. Bandwidth, channel count, frequency coverage and the waveform or scenario set all affect the hardware platform, so there is no single list price — but the structure is always one of these.
- Turn-key instrument Complete hardware, calibrated, with the control software and a twelve-month warranty. The usual choice.
- Rack-mount subsystem The same processing supplied as a board set or a chassis card for integration into your own test rack.
- FPGA image for your hardware If you already own a suitable FPGA and converter platform, we can port the system image onto it as a services engagement.
- Custom configuration Additional impairments, an extra waveform, a different fronthaul — specified, quoted and verified like any other design engagement.
Tell us what you need to test.
Bandwidth, channel count, the standard involved and whether the loop is closed. That is enough for us to tell you which configuration fits.