Digital front-end cores

Closed-loop pre-distortion for power amplifiers driven close to compression. The datapath applies a memory-polynomial correction to the transmit stream; a separate estimation engine observes the coupled feedback path and solves for new coefficients in the background, so coefficient updates never interrupt transmission. Model structure and memory depth are compile-time parameters, letting you trade correction quality against DSP consumption per product.

• Generalised memory polynomial (GMP) and dynamic deviation reduction models
• Background coefficient estimation — no transmit interruption
• Indirect and direct learning architectures, selectable
• Declared headroom, so it sits behind any crest-factor reduction stage
• Per-carrier gain and delay alignment for multi-band transmitters
• Thermal drift tracking with configurable adaptation rate

Key specifications

Instantaneous BW	Up to 400 MHz signal, 5× observation
ACLR improvement	> 20 dB typical on a Doherty PA
Model order	Non-linear order 3–11, memory depth 1–8
Adaptation time	< 2 ms to convergence from cold start
Carriers	Single-band and dual-band configurations
Interfaces	AXI4-Stream data, AXI4-Lite control
Typical FPGA	21 kLUT, 210 DSP @ 491.52 MHz

Receive-side counterpart to ALF-RF-DUC. Each carrier has its own NCO, mixer and decimating filter chain, so a single wideband ADC stream can be split into independently tuned narrowband channels — the usual arrangement for multi-band receivers and for monitoring receivers that must watch several carriers at once.

• Up to 16 independently tuned carriers from one input stream
• Decimation factors 2 – 4 096 with per-carrier settings
• Per-carrier NCO with 48-bit frequency resolution
• Independent digital gain and headroom control per carrier
• Overflow and saturation reporting at every stage
• Real-time carrier retuning with phase-continuous option

Key specifications

Input rate	Up to 491.52 MSPS per stream
Carriers	1 – 16 per instance
Decimation	2 – 4 096, independent per carrier
Tuning resolution	48-bit NCO, < 2 mHz at 491.52 MSPS
Alias rejection	Configurable, typically 80 – 100 dB
Interfaces	AXI4-Stream data, AXI4-Lite control
Typical FPGA	8 kLUT, 72 DSP for 4 carriers @ 491.52 MHz

Interpolates baseband carriers to the DAC sample rate and places each at its assigned centre frequency. The filter chain is generated at elaboration time from the requested rate change and stopband attenuation, so you get the minimum arithmetic that meets the specification rather than a fixed cascade sized for the worst case.

• Up to 16 independent carriers summed to one output stream
• Interpolation factors 2 – 4 096, non-power-of-two supported
• Filter chain synthesised from stopband and ripple requirements
• Per-carrier gain, phase and frequency, updated without a glitch
• Optional inverse-sinc correction for DAC roll-off
• Deterministic, reported latency for calibrated transmit chains

Key specifications

Output rate	Up to 491.52 MSPS per stream
Carriers	1 – 16 per instance
Interpolation	2 – 4 096
Stopband	Configurable, typically 80 – 100 dB
Passband ripple	< 0.05 dB peak-to-peak
Interfaces	AXI4-Stream data, AXI4-Lite control
Typical FPGA	7 kLUT, 64 DSP for 4 carriers @ 491.52 MHz

Converts between sample rates whose ratio is not rational, or is rational with an inconvenient denominator — the usual case when a converter clock and a symbol rate are derived from unrelated references. The Farrow structure makes the resampling ratio a run-time input, so it can also close a timing-recovery loop directly.

• Arbitrary, run-time-variable resampling ratio from 0.25 to 4.0
• Lagrange or minimax-optimised polynomial coefficients
• Polynomial order 2 – 6, selected at build time
• Usable as the interpolator inside a symbol-timing loop
• Image rejection > 90 dB over the useful passband
• Multi-channel mode with shared arithmetic

Key specifications

Ratio	0.25 – 4.0, arbitrary and run-time variable
Structure	Farrow, polynomial order 2 – 6
Image rejection	> 90 dB (order 5, 80 % passband)
Ratio resolution	32-bit fractional
Throughput	1 sample per clock, up to 500 MHz
Interfaces	AXI4-Stream data, AXI4-Lite control
Typical FPGA	1.4 kLUT, 18 DSP @ 400 MHz