RF and communications IP cores, built to close timing on the first pass.
AlfaRF builds FPGA and RTL based signal processing for the radio chain. We license it as IP cores — portable synthesisable VHDL, or a closed-box core where the source cannot be released, with bit-accurate models and a verification environment you can run on day one — and we build finished instruments on the same cores.
- 15
- Licensable cores across three product families
- 28 nm
- Smallest node with silicon-proven deployments
- < 4 wk
- Typical evaluation-to-integration cycle
- 100%
- Statement, branch and toggle coverage sign-off
Three families that cover the digital half of the radio
Every core ships as portable, vendor-neutral VHDL — or as a closed box, on the same deliverable set — with the same coding conventions and the same register map generator, so blocks from different families integrate without an adapter layer.
Wireless & Satellite Modems
Complete transmit and receive PHY chains for standards-based and proprietary waveforms.
- DVB-S2/S2X modulator & demodulator
- 5G NR base-station PHY
- QAM, PSK and CPM link modems
- CCSDS telemetry and configurable OFDM
Digital Front-End
Everything between the data converter and the baseband: rate change, correction and linearisation.
- Adaptive digital pre-distortion
- Multi-carrier digital up-conversion
- Multi-carrier digital down-conversion
- Arbitrary fractional resampling
Channel Coding & FEC
The encoders and decoders the satellite and cellular link budgets actually turn on.
- 5G NR and DVB-S2X LDPC encoding
- Layered normalised min-sum LDPC decoding
- Convolutional encoding and Viterbi decoding
- Up to 40 Gbps encode, 25 Gbps decode
Finished instruments, built on the same cores
Not every customer wants to integrate RTL. Two of our products are complete FPGA hardware systems — and because the processing inside is IP we wrote and characterised ourselves, the real-time behaviour is specified rather than hoped for.
RF Channel Emulator
Emulates the propagation environment in real time — multipath fading, Doppler, path loss, noise, interference and transceiver impairments — with sub-microsecond deterministic latency and bit-repeatable scenarios.
Vector Signal Generator
Generates standards-compliant waveforms live from real modem cores rather than replaying an IQ file, and runs entirely standalone — no host PC, no waveform memory limit, no per-waveform option keys.
alfacores does the board
We take the signal; our sister company takes everything it travels across. PCI Express with the data mover built in, converter links, Ethernet and the fabric between them — same coding conventions, same register discipline, same verification sign-off, so cores from the two catalogues drop into one design without a translation layer.
| Host interface | PCI Express Gen1–Gen5 with DMA, drivers included |
|---|---|
| Data movement | Multi-channel scatter-gather DMA |
| Converter links | JESD204B/C and LVDS converter interfaces |
| Networking | 10G–100G Ethernet with hardware UDP/IP |
| SoC fabric | AXI4 interconnect and register map generation |
| Systems | EVKits, and the PCIe Graphic Renderer |
Send us the hard part of your specification.
Symbol rate, SNR target, latency budget, resource envelope. We will tell you which core fits, what it costs in logic, and where it does not fit.